Field of the Invention
The embodiments of the invention generally relate to semiconductor structures, and, more particularly, to an improved silicon germanium heterojunction bipolar transistor and a method of forming the improved transistor.
Description of the Related Art
New communications and test applications require chips operating at ever-higher frequencies. While high frequency transistors are available in group III-V semiconductor materials (e.g., gallium arsenide (GaAs), gallium nitride (GaN), etc.), a silicon-based solution (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistors (HBTs)) would be less expensive and permit higher levels of integration than is currently available in with such group III-V semiconductor materials.
However, device scaling is also a concern and limitations in current process technology has limited scaling, both vertical and lateral, of such silicon germanium (SiGe) hetero-junction bipolar transistors (HBTs). Specifically, narrowing of the transistor base and collector space-charge region increases the current-gain cut-off frequency (Ft), but does so at the expense of the maximum oscillation frequency (Fmax) because of overlap between the collector and extrinsic base. Therefore, in conjunction with device size scaling, it is desirable to bring the collector region closer to the base region in order to enhance Ft by using a selective ion-implanted collector (SIC) pedestal (e.g., as illustrated in U.S. Pat. No. 6,846,710 issued to Yi et al., on Jan. 25, 2005 and incorporated herein by reference). However, current process technology cannot make such an SIC pedestal narrow enough to cause minimal overlap with the extrinsic base. Furthermore, interstitials (i.e., damage, defects, etc.), which are created at the SiGe HBT base-collector interface as a result of the prior art formation processes (i.e., ion-implantation), allow unwanted diffusion of the implanted dopants.